Techniques for Yield Enhancement of VLSI
نویسندگان
چکیده
For VLSI application-specific arrays and other regular VLSI circuits, two techniques are available for yield enhancement, namely defect-tolerance and layout modifications. In this paper, we compare these two yield enhancement approaches by using adders as an ezample. Our yield projections indicate that the layout modification technique ia more eficient when the defect density is low, while reconfigtrration is more eficient for a high defect density. However, fmm the point of the view of effective yield, the layout modification is superior to defect tolerance in the practical range of defect density.
منابع مشابه
Techniques for Yield Enhancement of VLSI Adders 1
For VLSI application-speciic arrays and other regular VLSI circuits, two techniques are available for yield enhancement, namely defect-tolerance and layout modiications. In this paper, we compare these two yield enhancement approaches by using adders as an example. Our yield projections indicate that the layout modiication technique is more eecient when the defect density is low, while reconngu...
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